
module IF_ID_reg(
    input wire clk,
    input wire flag,
    input wire pc_replace,
    input wire [31:0] idata_in,
    input wire [31:0] iaddr_in,
    output reg [31:0] FD_idata_out,
    output reg [31:0] FD_iaddr_out
);

    always @(posedge clk) begin  //posedge clk
        if (flag == 1) begin
            if (pc_replace == 1) begin
                FD_idata_out <= 32'b00000000000000000000000000010011;
            end 
            else begin
                FD_idata_out <= idata_in;
                FD_iaddr_out <= iaddr_in;
            end
            
        end
        else begin
            FD_idata_out <= 32'b00000000000000000000000000010011;
            FD_iaddr_out <= iaddr_in;
        end
        //else FD_idata_out <= 32'b00000000000000000000000000000000;
        
    end

endmodule